Freescale Semiconductor /MK30D7 /SIM /CLKDIV2

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Interpret as CLKDIV2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Description

System Clock Divider Register 2

Links

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